A NFET (of unknown gate material) has the ID -vs -VDS curve shown below for VGS =4 V and
VBS =0 V . The threshold voltage VTN of the device is 1 V when VBS =0 V .
Assume:
W=25×10-4cm
L=10×10-4cm
�!”=3.45×10-13 F/cm
tox=10-6 cm
Na=1017cm-3
a) What is the drain-to-source voltage at which the device saturates when VGS =4 V
b) What is the electron mobility (cm2/V-s) in the channel?
c) What is the inversion layer sheet charge density (in C/cm2) in the FET channel at the
source end when VGS=4 V and VDS=1V and VBS =0V ?
d) What is the inversion layer sheet charge density (in C/cm2) in the FET channel at
the drain end when VGS =4 V and VDS =1V and VBS =0 V ?
e) For the same bias conditions as in parts (c) and (d), what is the drift velocity of
electrons (cm/s) near the source end?
f) For the same bias conditions as in parts (c) and (d), what is the drift velocity of
electrons (cm/s) near the source end?
g) What is the inversion layer sheet charge density (in C/cm2) in the FET channel at the
source end when VGS =4 V and VDS =5 V and VBS =0 V ?
h) What is the inversion layer sheet charge density (in C/cm2) in the FET channel at
the drain end when VGS =4 V and VDS =5 V and VBS =0 V
Consider the following NFET amplifier:
In the following parts, assume that the load resistor RL is NOT connected to the output.
a) Generally one would like to keep the resistor R large. But if it is too large, the FET
could go into the linear region for a given desired value of the DC drain current ID .
Suppose you are at liberty to choose any value of the DC input bias voltage VIN . For
every value of VIN above VTN the value of the resistor R has to be within a range in
order to keep the FET in the saturation region of operation. For values of VIN
between 0.5 and 2.5 Volts, find the maximum (Rmax ) and the minimum (Rmin) values
of the resistance R needed to keep the FET working the saturation region. Plot Rmax
and Rmin on the same plot as a function of VIN
b) Suppose you need to the keep the DC voltage at the output VOUT equal to 1.5 V. And
you also need to keep the small signal gain, and therefore gm , reasonably high, so
you choose ID=200 mA . What should be the values of the resistor R and the input
bias voltage VIN needed to meet these objectives? Or can these objectives even be
met while keeping the FET in the saturation region?
c) With the numerical value of the resistor as in part (b), and a varying input voltage
VIN , what are the maximum and the minimum values of the output voltage VOUT such
that the FET remains in the saturation region?
d) With the value of the resistor as in part (b), what are the maximum and the
minimum values of the input voltage VIN such that the FET remains in the
saturation region?
e) With the value of the resistor as in part (b), compute and plot (sketches not
acceptable) the transfer curve VOUT-vs-VIN and indicate regions in which the FET is in
the cut off, linear, and saturation regions.
f) With the value of the resistor and the biasing scheme as in part (b), what is the open
circuit small signal voltage gain Av =vout/vin (i.e. the voltage gain with the load
resistor disconnected)? Need a numerical number as an answer and not just a
formula.
Now suppose the load resistor RL is connected to the output of the amplifier. Its presence
will change things significantly.
a) Suppose your biasing scheme, including values of VIN and R are as in part (b) above.
With the load resistor now connected, what is the new output voltage VOut? Hint: it is
not going to be 1.5 Volts anymore. And what is IOUT ?
Lesson: loading can affect the DC biasing of an amplifier!
b) Suppose your biasing scheme, including values of VIN and R are as in part (b) above.
With the load resistor now connected, what is the small signal voltage gain
Av=vout/vin? Need a numerical number as an answer and not just a formula. Has it
decreased or increased compared to the case when the load resistor was not
connected?
Lesson: loading can affect the small signal performance of an amplifier!